Phase locked loops have always presented a challenge to simulation software because of the convergence problems associated with the control loop. Not so for SpiceAge.
The demonstration network, PLL.CMP is fully functioning phase locked loop based around a type 1 (exclusive OR) phase detector and a lead-lag compensation filter network to ensure stability.
When you perform a transient response, you will see the VCO frequency rise and synchronise with the input signal. Also shown is the error signal - it is quite instructive to watch this as the loop actually comes into lock.
